Build your first SystemVerilog + UVM testbench in one weekend — with an engineer who does this at Google.
A 2-day live Mastermind for final-year ECE students and 0–2 YOE DV engineers. Leave Sunday evening with a running testbench on your laptop — not a certificate.
Built by Rishi · 11 yrs silicon verification at Google & Synopsys
The gap this weekend closes
Most learners never see what “verified” looks like.
You read the books, watched the lectures, and still can't tell if your testbench is any good. That's not a you problem. It's what the weekend fixes.
Video courses don't show what “done” looks like.
They teach syntax and demo a scripted pass. They don't show you a failing seed, a waveform diff, or an engineer deciding what to check first.
College labs don't produce a running testbench.
Assignments end at “simulation ran.” Nobody closes coverage, nobody files a bug with a reproducer, nobody signs anything off.
Tutorials teach syntax, not the engineer's mental model.
UVM has 40 classes. You only need the 6 that carry real work. A tutorial won't tell you which — an engineer in the room will.
What you leave Sunday with
A working testbench, on your laptop — not a certificate.
On your machine
- A working
tb_top.svrunning under Verilator - A UVM skeleton that drives one transaction end-to-end
- A GTKWave recording of your first passing simulation
- A clean Git repo you can push to your public GitHub
In your head
- The mental map for what “verified” actually means
- Where RTL → DV → sign-off fits inside a real silicon team
- Which 6 UVM classes carry 90% of real work
- A 1-page “what to do next” map, handed out Sunday 4 PM
This is the Mastermind deliverable. It is intentionally scoped to 2 days.
The weekend · 4 sessions
2 days. 4 sessions. One working testbench.
Saturday and Sunday, 10 AM to 4 PM IST, live with Rishi. Same code editor on screen as yours. You build alongside; he watches and unsticks.
The DV Landscape & SystemVerilog Fluency
Where verification sits in the chip lifecycle, and the SV language surface you'll use all weekend.
+
The DV Landscape & SystemVerilog Fluency
Where verification sits in the chip lifecycle, and the SV language surface you'll use all weekend.
- Map RTL → DV → sign-off as it runs inside a real silicon team
- Read and write SV classes, interfaces, and clocking blocks
- Stand up a Verilator sim + GTKWave view on your laptop
- Run your first directed test against a dummy DUT
- [TBD: Rishi — one anecdote from a real project]
Artifact: rtl/tb_top.sv · first passing sim on your laptop
UVM in One Afternoon
The UVM mental model, stripped of jargon, built in front of you.
+
UVM in One Afternoon
The UVM mental model, stripped of jargon, built in front of you.
- Trace data: sequencer → driver → DUT → monitor → scoreboard
- Register a component with uvm_config_db
- Run a passing UVM sequence against a toy DUT
- Read a UVM report log and know where to look first
- [TBD: Rishi — one anecdote]
Artifact: uvm/uart_agent.sv
Protocol, Coverage, Assertions
The “what does done mean” session — how working engineers call a block verified.
+
Protocol, Coverage, Assertions
The “what does done mean” session — how working engineers call a block verified.
- Extract protocol invariants from a UART-style datasheet
- Write constrained-random sequence items
- Instrument a covergroup and read a coverage report
- Write a first SVA for a protocol invariant
- [TBD: Rishi — one anecdote]
Artifact: uvm/uart_cov.sv, uart_sva.sv
Debug, Regress & What Comes Next
Working-engineer muscles: diagnose from waveform, file a bug, close the loop.
+
Debug, Regress & What Comes Next
Working-engineer muscles: diagnose from waveform, file a bug, close the loop.
- Diagnose a failing seed from waveform alone
- File a bug with a minimal reproducer + RCA
- Read a Makefile-driven regression result
- Leave with a clean Git repo and a next-steps map
- [TBD: Rishi — one anecdote]
Artifact: bugs/bug-0001.md, Makefile
How the weekend runs
Not a video library. Not a lecture. A live build.
You ship code while Rishi watches. Stuck? He unsticks you on the spot — same timezone, same screen, no ticket queue.
Live build
Rishi codes on screen. You follow along on your laptop, at the same pace, with the same tools. When his sim passes, yours should too.
Over-the-shoulder review
Stuck? Paste your terminal output in Discord. Rishi or a peer unsticks you within 10 minutes during session hours — not 24 hours later.
Peer pods of 3
You're paired with 2 other engineers on day 1. You debug each other's code between sessions. First signal of a real DV team: the people next to you.
Tools of the trade
100% open-source. Zero licence cost. Runs on your laptop.
We help you install everything in a Day-0 setup before the weekend starts. Linux, macOS, or Windows with WSL.
Who's teaching
Reviewed by a working verification engineer. Not a TA.
11+ years in silicon verification.
Currently at Google. Previously at Synopsys. Shipped VIPs and signed off blocks on UCIe, I3C, SAS, and Fibre Channel. Runs cohort 01 personally — no TAs, no ghost-writing.
Teaches the way he reviews juniors on real projects: specific, direct, one bug at a time. If your repo needs a rewrite, you'll hear it. If it's clean, he'll say that in one line.
“Most people don't struggle with syntax. They struggle with deciding what to check first. This weekend is about that.”
Fit
We'd rather you not come than come and feel cheated.
✓ For you, if
- You're a final-year ECE / VLSI M.Tech student
- You're a DV engineer with 0–2 YOE wanting real depth
- You're self-taught and want an engineer in the room
- You can block Saturday & Sunday 10 AM – 4 PM IST
- Your laptop runs Linux or WSL with 8+ GB RAM
— Not for you, if
- You're a senior DV engineer — you'll be bored
- You want a placement guarantee — we don't issue them
- You want a recorded self-paced course — this is live-only
- You can't commit to both days in full
- You need commercial EDA licences — we use open-source
Self fit-check · 30 seconds
Three honest questions before you apply.
01Can you block both days of the weekend, 10 AM — 4 PM IST?
02Laptop that runs Linux / WSL with 8+ GB RAM?
03Comfortable reading a datasheet in English?
Testimonials
No stock quotes. No invented faces.
[PLACEHOLDER]
Cohort 01's Mastermind runs 13–14 Jun 2026. Real graduate quotes, with names and GitHub links, land here after the weekend.
Pricing
One fee. One weekend. No upsells on this page.
ReyaTech VLSI Mastermind
SV + UVM Weekend
2-day live build · Saturday & Sunday · 10 AM – 4 PM IST
₹499
Inclusive of GST · one-time · INR
What's included
- 4 live sessions with Rishi (two on Sat, two on Sun)
- Mastermind repo template, ready to clone
- Day-0 toolchain setup help
- Discord access for the weekend cohort
- Peer pod of 3 engineers for the weekend
- A 1-page “what to do next” map, Sunday 4 PM
FAQ
Eight honest answers.
Do I need commercial EDA licences?
What if I miss one of the 4 sessions?
How much time do I need on Saturday + Sunday?
Is there a placement guarantee?
Do I get a certificate?
Can my employer sponsor the weekend?
What's the refund policy?
Is there something after the Mastermind?
For chip companies
Training DV engineers at your company?
We run closed weekend Masterminds for teams of 8–15, under NDA, with your IP and your toolchain. No logo wall until we have real customers.
What comes next · deliberately light on detail
Engineers who ship a working testbench by Sunday evening are invited to an intensive programme that takes the same testbench all the way to a sign-off-ready IP block — coverage, assertions, debug, CI, and a reviewed report. We pitch it on Sunday inside the Mastermind, not here. No curriculum on this page. If you're already sure, come to the weekend first.
Apply for cohort 01
One weekend. One working testbench. One engineer in the room.
Rishi reads every application and replies within 48 hours — yes or no, with a reason. Applications close Fri 30 May 2026.